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National Semiconductor Embedded Microcontrollers


National Semiconductor Embedded Microcontrollers
CompactRISC and COP8 Flash Microcontrollers,
Manufacturers an excellent very low power microcontroller, the CompactRISC. Besides being feature-rich, available modules include Bluetooth, USB, and CAN.

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CompactRISC General Overview

The CompactRISC architecture was created from the ground up as a scalable architecture, covering the 16-bit embedded processor domain, while providing the best of RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architectures. The CompactRISC architecture is enhanced with some typical CISC features, like variable instruction set and direct memory bit manipulation to make it even more effective for embedded applications. A CompactRISC core delivers high performance while maintaining low power consumption, small die size and high code density. Through its modular bus architecture the CompactRISC technology allows designers to build performance-tailored functionality around the CompactRISC core. A separate bus for the on-chip peripheral allows a system-on-a-chip designer to use the same on-chip peripherals and I/O with all CompactRISC derivatives. With common processor architecture and software development tools a software designer can feel comfortable to write identical code for any of the CompactRISC cores.  Key Characteristics 

  • Reduced Power: Suitable for portable applications    
  • High Performance: Delivering the right performance to meet most embedded application needs    
  • Small Code/Data Size: Avoiding the typical code/data expansion of RISC processors    
  • Minimal Die Size: Freeing space for on-chip application-specific peripherals and memory    
  • Portability & Scalability: Common architecture and development tools for all CompactRISC derivatives    
  • Modular bus architecture: Sharability of peripherals between all CompactRISC derivatives    
  • Debugging Features: On-chip debugging support    
  • Multi-core Solution : A proven system-on-a-chip integration of multiple RISC and DSP    
  • Licensing: Available in Synthesizable Verilog HDL 
 Optimized Pipelining, Reduced Concurrency Logic, and Smaller Bus Interfaces

Traditional RISC architectures are driven by the need to squeeze every bit of execution time from a fast system clock, hence typically trading silicon efficiency for instruction execution efficiency. Overlapping pipelines and highly parallel concurrent logic achieve this goal, but at a cost: far more on-chip transistors and greatly increased die size, at a relatively small performance gain. Because the performance needs of embedded controllers are quite different from those of workstation MPUs, the pressure to squeeze clock performance through every available design trick is lessened. With fewer pipeline stages (just three compared to five or more) the CompactRISC architecture eliminates a large amount of costly pipeline control logic. This shorter pipeline organization allows elimination of branch prediction mechanisms and bypass registers, yet the CompactRISC architecture maintains an acceptable overall performance level for embedded system needs. 

 

Generic Block Diagram


Traditional RISC systems have also utilized large off-chip memory and I/O, so on-chip bus interface units were large and complex. Because embedded systems typically use on-chip memory wherever possible, the CompactRISC architecture was designed with a minimal core bus controller (CBC) for on-chip memories. A bus interface unit (BIU) for external memory accesses is added only when off-chip memory is needed. A separate peripheral bus controller (PBC) is optimized for on-chip I/O. This approach yields maximum resource flexibility with minimum silicon overhead. 

 Reduced Memory Requirements

 

Code Size Comparison Graph

To simplify instruction decoder design, RISC architectures have traditionally employed fixed-width instructions. For 32-bit RISC systems, every instruction is four bytes. In CISC systems, a variable instruction length is used, resulting in smaller code sizes for a given application. CompactRISC technology utilizes variable instruction widths with fixed coding fields within the instruction itself. For example, the opcode field is always in the first 16 bits with additional bytes as required for immediate values. Instructions for the CompactRISC architecture may be 2, 4 or 6 bytes long, but basic instructions are only 2 bytes long. This permits optimized instruction processing by the instruction decoder, and results in a smaller code size. Code generated for the CompactRISC core is comparable to CISC code size, or typically 25 to 50 percent smaller than code generated for leading 32-bit RISC CPUs. Another advantage this provides, is the ability to generate performance with lower pin-counts or lower-bandwidth busses - again a trait of an embedded system. 
Data Size Comparison Graph

In addition, 32-bit RISC processors store registers and addresses on the stack as 32-bit entities and deliver high performance only when aligned 32-bit data is used. Non-aligned data significantly hampers performance. Intermediate results are stored in memory as 32-bit values and registers are saved as 32-bit operands on the stack. CompactRISC instructions operate on 8-, 16- and 32-bit data. Nonaligned accesses are allowed. Dedicated data type conversion instructions speed data access to mixed size data. With smaller code size, and variable length instructions and data, the CompactRISC family provides more efficient use of smaller, lower cost, lower bandwidth memories.
 Enhanced CompactRISC 16-bit Instructions and Features

National has now created a second generation 16-bit implementation to provide expanded options for system designers. The new implementation provides for: 

  • Expanded program address space of 2 Mbytes   
  • Atomic Memory Direct Bit Manipulation of single bits to efficiently handle semaphores, I/O triggers, etc.   
  • Multiple-register save and restore instructions   
  • Multiple push and pop instructions   
  • Addition of a hardware multiplier unit for fast 16-bit multiplication   
  • On chip debug features, including hardware breakpoint support   
  • Synthesizable Verilog HDL format.

 

CR16B Block Diagram

To ensure a seamless migration path for existing CompactRISC users, the new 16-bit design also allows for two programming models -- one that supports the new 2 Mbyte program address space and a smaller model providing backward compatibility with previous 16-bit CompactRISC core. In addition, the new implementation supports a variety of debug and self-test features, including programmable hardware breakpoints for instructions and data, plus built-in hooks for in-system emulation (ISE) equipment. 
 Registers
Register Diagram

General purpose registers are used for high-speed general storage, as in holding variables, addresses or index values. For instance, one register is usually used as a pointer to the program run-time stack, while others may be used as return addresses from subroutines. If a general purpose register is specified as an operand that is 8 or 16 bits long, then only the lower bytes of the register are used, with the higher bytes not referenced or modified. 

The configuration resgister (CFG) holds control bits, determining the mode in which the core operates. Specifically for the new 16-bit implementation, it controls the dispatch table entry size, allowing for small/large memory-model programmability. The processor status register (PSR) holds status information and determines operating modes for the processor. Bits in this register serve as flags indicating the results of intermediate and final ALU operations such as carry bits, zero indications, and negative comparison bits. Also included are interrupt masking and enabling bits and trace bits for debugging. Processors designed with the CompactRISC architecture include hardware for a variety of debugging and self-test features, as well as hooks for external ISE equipment for tracing instruction execution and pipeline sequencing. 

Three debug-specific registers (DCR, DSR, CAR) control the CompactRISC on-chip debug module, allowing breakpoints on instruction fetch, data-read and data-write. For more information, see the Debug Support below.

 Debug Support

The CompactRISC architecture provides on-chip, hardware breakpoint instruction tracing, soft breakpoints via breakpoint instructions and external ISE support. 

Three debug-sepcific register control the hardware debug module. In addition for the new 16-bit implementation, there is enhanced external instruction fetch breakpoint support, allowing breakpoints on instruction fetch or data read/write according to address-compare. In general, the debug control register (DCR) controls the various debug feature activation, the debug status register (DSR) holds the indication bits, identifying the source of breakpoint. The compare-address register (CAR) contains the address to be matched for breakpoint by the debug module.Instruction tracing is used during debugging to single-step through a program. Two bits in the PSR enable and generate trace traps. In addition, a breakpoint instruction (EXCP BPT) can be used to stop the execution of a program at specified instructions, allowing the debugger to examine the status of the program and internal registers. The CompactRISC architecture also supports an input pin that causes an ISE interrupt. The core processor then provides status signals that are activated upon completing an instruction and, in some of the cores, also has on-chip hardware breakpoint support for data and address values. In addition, National Semiconductor's incorporation of JTAG interfaces allows for efficient design and debug of multiple-core implementations, such as two CompactRISC cores, integration of DSP cores, etc. within a single die. 

 Development Tools
High-level development tools are essential to rapid, modern design. The CompactRISC architecture is well supported with a comprehensive C-based development and debug environment available from National and third party vendors. Key software development components include an optimizing C compiler, a macro assembler, run-tim libraries, librarian and a graphical source-level debugger including enhanced simulation capabilities. In addition, support for debugging of multiple CompactRISC/DSP cores on a single die, come from the use of an integrated graphical debugger. On the hardware side, the CompactRISC architecture has modular ISE (In System Emulator) support from third-party development system vendors, and various development boards for all current product offerings. As a package, these tools simplify the task of designing and developing advanced embedded systems in high level languages such as ANSI-C.
 Summary
The CompactRISC architecture enables RISC processors optimized for performance, power consumption and die size, bringing the significant advantages of RISC to the embedded systems market. Unlike traditional RISC processors that are optimized to execute large, memory-intensive workstation applications, the CompactRISC technology family of embedded RISC processors are cost-effective, memory-efficient, high-performance silicon solutions. They are a silicon-efficient means of integrating high-performance RISC processors with local memory and I/O to produce advanced compute-intensive embedded systems. 

Key RISC advantages include a streamlined instruction set optimized HLL compilers; single-cycle instruction execution; and fast, multistage pipeline structures. To this, the CompactRISC processors add compact code generation, efficient RAM utilization, low-cost silicon implementations and a scalable architecture that spans the range from 8-bit, to 16-bit, 32-bit and 64-bit versions. 

Over the past three years, the CompactRISC architecture has firmly established itself by filling a previously unmet market gap -- those applications that require the performance of RISC but cannot afford the processing and cost overheads of 32-bit RISC implementations. The 16-bit member of the CompactRISC family has been particularly popular with designers because of its optimal balance of cost and performance, plus the ability to combine its small core die size with other key on-chip functions. With the additional features included in the new 16-bit CompactRISC processors, designers can now take advantage of an expanded code space and even more features targeted specifically for embedded implementations. Plus, with built-in scalability, the migration path to 32-bit implementations, using the same basic CompactRISC architecture, is always open. 

 

CompactRISC is a trademark of National Semiconductor Corporation 

 

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Created:20-Feb-2003,
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