Jul 29, 2010 - 2:55:27 PM
STMicroelectronics has introduced the ST SPEAr1310 microcontroller, a dual-core microcontroller with a DDR3 memory interface and plenty of networking peripherals.
The 32-bit ST SPEAr1310 microcontroller has two ARM Cortex-A9 cores (ARM926EJ-S) and a DDR3 (Third-generation double-data rate) memory interface. It is manufactured in STMicroelectronics' 55nm HCMOS process technology.
The ST SPEAr1310 microcontroller incorporates the ST Network-on-Chip (STNoC) technology, which internally networks the microcontroller's on-chip peripheral & IP blocks in a "spidergon" arrangement, where each on-chip peripheral & IP block is connected to adjacent blocks, rather than the traditional common bus arrangement. This results in a more efficient architecture.
On-chip configurable logic is also available, for up to 1300 Kgates.
The ST SPEAr1310 microcontroller with dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent.
Spear SPEAr1310 Features
Key features of the STMicroelectronics ST SPEAr1310 microcontroller include:
- Two ARM Cortex-A9 cores (ARM926EJ-S)
- 32 KByte Boot RAM
- Two Giga/Fast Ethernet MACs (for external GMII/RGMII/MII PHY)
- Three 10/100 BaseT Ethernet MACs
- three PCIe/SATA Gen2 links (with embedded PHY)
- One 32-bit PCI expansion bus (up to 66 MHz)
- Two USB 2.0 ports with PHY
- One USB 2.0 OTG port with PHY
- Two CAN 2.0 a/b interfaces
- Two TDM/E1 HDLC controllers with 256/32 time slots per frame respectively
- Two HDLC controllers for external RS485 PHYs
- Six USARTs
- Two I2C
- Two I2S
- One SPI
- HD Display controller with Touchscreen and Overlay windows capabilities
- Memory Card I/F
- Security HW Accelerator
- Secure Boot and Key Storage capabilities
- Many Power saving features
Samples of the ST SPEAr1310 are now available upon request to lead customers for evaluation and prototyping. Pricing is not yet available - check back for updates to this article!
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